지원사업
학술연구/단체지원/교육 등 연구자 활동을 지속하도록 DBpia가 지원하고 있어요.
커뮤니티
연구자들이 자신의 연구와 전문성을 널리 알리고, 새로운 협력의 기회를 만들 수 있는 네트워킹 공간이에요.
논문 기본 정보
- 자료유형
- 학술저널
- 저자정보
- 저널정보
- Korean Institute of Information Scientists and Engineers Journal of Computing Science and Engineering Journal of Computing Science and Engineering Vol.14 No.4
- 발행연도
- 2020.12
- 수록면
- 146 - 153 (8page)
- DOI
- 10.5626/JCSE.2020.14.4.146
이용수
초록· 키워드
오류제보하기
The fingerprint recognition system has a scheme in which the fingerprint sensor and the algorithm are separated. It is ineffective to operate a total fingerprint algorithm with various simple iterations using only the software environment. This paper proposes an effective fingerprint identification system with VLSI (very large scale integration) hardware architecture for Gabor filter and thinning processing. These two steps occupy the largest portion of CPU processing time in minutiae based fingerprint recognition algorithms. In this paper, we analyze the step-by-step operation of the algorithm using an ARM emulator. We implemented a VLSI logic circuit for hardware processing of Gabor filters and thinning in RTL. The logic is also synthesized and the layout is performed based on automatic placement-routing and post-simulation is performed in the 250n 6-metal CMOS process. The result is compared with the data of a conventional study. The proposed circuit is verified to reduce the algorithm processing time by 73%.
목차
Abstract
I. INTRODUCTION
II. ANALYSIS OF THE ALGORITHM
III. LOGIC DESIGN
IV. CONCLUSION
REFERENCES
참고문헌 (7)
참고문헌 신청
H. Yeo, “Touch fingerprint sensor based on sensor cell isolation technique with pseudo direct signaling,” International Journal on Smart Sensing and Intelligent Systems, vol. 12, no. 1, article no. 1, 2019.
L. Hong, Y. Wan, and A. Jain, “Fingerprint image enhancement: algorithm and performance evaluation,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 20, no. 8, pp. 777-789, 1998.
S. M. Jung, J. M. Nam, D. H. Yang, and M. K. Lee, “A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller,” IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1745-1750, 2005.
S. M. Jung, “Design of low power and high speed CMOS fingerprint sensor,” International Journal of Bio-Science and Bio-Technology, vol. 5, no. 2, pp. 1-16, 2013.
H. Hassan and H. W. Kim, “CMOS capacitive fingerprint sensor based on differential sensing circuit with noise cancellation,” Sensors, vol. 18, no. 7, article no. 2200, 2018.
L. Hong, Y. Wan, and A. Jain, “Fingerprint image enhancement: algorithm and performance evaluation,” IEEE Transactions on Pattern Analysis and Machine Intelligence, vol. 20, no. 8, pp. 777-789, 1998.
S. M. Jung, J. M. Nam, D. H. Yang, and M. K. Lee, “A CMOS integrated capacitive fingerprint sensor with 32-bit RISC microcontroller,” IEEE Journal of Solid-State Circuits, vol. 40, no. 8, pp. 1745-1750, 2005.
S. M. Jung, “Design of low power and high speed CMOS fingerprint sensor,” International Journal of Bio-Science and Bio-Technology, vol. 5, no. 2, pp. 1-16, 2013.
H. Hassan and H. W. Kim, “CMOS capacitive fingerprint sensor based on differential sensing circuit with noise cancellation,” Sensors, vol. 18, no. 7, article no. 2200, 2018.
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